Entries from December 2008 ↓

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The bus arbitrer may be the processor or a separate unit connected to the bus. In this case the processor is normally the bus master unless the the processor grants bus mastership to one of the DMA controllers. The DMA controller indicates that it needs to become the bus master by activating the Bus request line.  The signal on the Bus Request line is logical OR of the bus requests from all the devices connected to it. When Bus Request is activated, the processor activates the Bus Grant signal, BGI indicating to the DMA controllers that they may use the bus when it becomes free. This signal is connected to all DMA controllers using a daisy chain arrangement. Thus if DMA controller 1 is requesting the bus, it blocks the propagation of the grant signal to other devices. Otherwise, it passes the grant downstream by asserting BG2.

The device that is allowed to initiate data transfers on the bus at any given time is called the bus master. When the current master relinquishes the control of the bus another device can acquire the status. Bus arbitration is the process by which the next device to become the master of the bus is selected and the bus mastership is transferred to it. The selection of the bus master must tale into accounts the needs of various devices bt establishing a priority system for gaining access to the bus.

There are two approaches to the process called bus arbitration. They are centralised bus arbitration and distributed bus arbitration. In centralized arbitration a single bus arbitrer performs the required arbitration.In distributed arbitration all the devices participate in the selection of the bus master.

Although a DMA controller can transfer data without intervention by a processor its operation must be under the control of a  program executed by the processor. To initiate the transfer of a block of words, the processor sends the starting address, the number of words in the block, and the direction of the transfer. On recieving this information, the DMA controller proceeds to perform the required information. When the entire block has been transferred the controler informs the processor by by raising an interrupt signal.

When a DMA transfer is taking place, the program that requested the transfer cannot continue,and the processor can be used to execute another program. After the DMA transfer is completed the processor can return to the program that requested the transfer. I/O operations are always performed by the operating system of the computer in response to a request from an application program.

An instruction to transfer input or output data is executed only after the processor determines the I/O devices is ready. To do this, the processor determines whether the in-put or output device is ready. To do this, the processor either polls a status flag in the device interface or waits for the device to send an interrupt request. In either case, considerable overhead is incurred, brcause several program instructions must be executed for each data word transferred. In addition to polling the status register of the device, instructions are neede for incrementing the memory address and keeping track of he word count. When interrupts are used there is additional overhead associated with saving and restoring the program counter and other state information. To tranfer large blocks of data at high speed, an alternative approach is used. A special control unit may be provided to allow transfer a block of data directly.