Centralised Arbitration

The bus arbitrer may be the processor or a separate unit connected to the bus. In this case the processor is normally the bus master unless the the processor grants bus mastership to one of the DMA controllers. The DMA controller indicates that it needs to become the bus master by activating the Bus request line.  The signal on the Bus Request line is logical OR of the bus requests from all the devices connected to it. When Bus Request is activated, the processor activates the Bus Grant signal, BGI indicating to the DMA controllers that they may use the bus when it becomes free. This signal is connected to all DMA controllers using a daisy chain arrangement. Thus if DMA controller 1 is requesting the bus, it blocks the propagation of the grant signal to other devices. Otherwise, it passes the grant downstream by asserting BG2.